1. Field of the Invention
The present invention relates to pulse level correcting circuits, and more particularly to a pulse level correcting circuit which improves the level of a pulse signal on the ground side.
2. Description of the Prior Art
In using a semiconductor integrated circuit (IC), particularly a digital IC for an electronic calculator, an electronic timepiece, etc., the prescribed input level need be taken into consideration. At present, MOS (metal-oxide-semiconductor) IC's having such merits as high degree of integration and low power consumption are often employed in the uses of this field. Among the MOS IC's, the so-called silicon gate MOS IC in which polycrystal silicon is used for the gate electrode of a FET (field-effect transistor) has such merits as high-speed operation and low power consumption owing to its low threshold voltage characteristic, and it is recently in the limelight. On the other hand, however, the low threshold voltage characteristic has raised the problem of the norm of voltage levels on the ground potential side (high levels V.sub.IH in P-channel enhancement mode MOS transistors).
In more detail, the higher input level V.sub.IH need be confined below the threshold voltage (in absolute value) in order to prevent the transistor from operating erroneously. With lowering in the threshold voltage by the adoption of the silicon gate technique, it has become necessary to lower the higher input level V.sub.IH. In particular, in a flip-flop, a shift register, a memory circuit, etc., employing transfer gate MOS FET's of the clock drive, when the higher level V.sub.CPH of a clock pulse exceeds the threshold voltage even slightly, the storage operation is greatly affected.